A field effect transistor (“FET”) typically has a doped source region and a doped drain region separated by an oppositely doped, or intrinsic, region between them. By application of a suitable field from a gate, it is possible to form a conducting channel in this region. The field strength required to form this conducting channel is sometimes called the “threshold” of the transistor.
A field effect transistor with a high threshold will tend to have low leakage current. Such transistors are desirable for use in implementing features that operate during the device's stand-by mode.
In contrast, a transistor with a low threshold will tend to have a higher drive current. These are typically used when implementing features that require high performance or that operate only when the device is actively being used.
It is apparent that a tradeoff inherently exists between these two types of transistors. A typical integrated circuit that uses planar FETs will often have both types of transistors present.
It is known how to make transistors of either type. It is also known how to make planar transistors of both types on the same integrated circuit.
A difficulty that arises is that of making planar transistors smaller. Although, in a MOSFET, one can physically make the channel between source and drain shorter, short-channel effects limit the practical channel length achievable. As a result, if the channel becomes too short it becomes difficult to turn off the transistor. This causes undesirable properties, such as high leakage current.
The difficulties can be overcome with three-dimensional transistors, such as FinFETs. In FinFETs, the gate electrode surrounds multiple sides of a vertical channel, or fin. This provides greater control over the channel, which results in lower leakage.
However, the gate electrode only surrounds those parts of the channel that protrude above the shallow trench isolation. The fin body itself is buried within the shallow trench isolation and therefore is not surrounded. This gives rise to the possibility of leakage in the fin body under the shallow trench isolation and gate induced drain leakage associated with band-to-band tunneling at the drain/body interface. It is desirable to control this leakage current.
Experimental results available in the prior art suggest that the overall shape of the fin has no effect on the leakage current, but that changing the dimension of the fin width and height does. In particular, according to the prior art, making the base of the fin smaller will reduce leakage. However, making smaller fins is difficult, and the fin width is typically fixed to the technology node.
Another method for decreasing leakage in FinFETs is to retract the source and drain implants away from the channel. A disadvantage of this method is that the transistor inevitably consumes more area on a chip. This tends to undermine one of the advantages of using a FinFET in the first place. Another disadvantage is that FinFET fabrication methods generally work best when all transistors have the same footprint. If different FinFETs require different base sizes to implement transistors having different properties, the prospect of having such FinFETs formed on the same chip becomes more difficult.